The present invention forms part of the field of amplifiers, notably current amplifiers. Such amplifiers are advantageously utilized in switching matrices which are circuits or circuit assemblies having N signal inputs and P signal outputs and which have as a peculiarity that each of the P outputs may be connected to each of the N inputs on command.
In such a matrix current paths having considerable lengths are to be used for connecting the inputs to the outputs, said lengths being all the larger as the number of inputs and outputs, and thus the complexity of the matrix under consideration, are larger. Generally, it will be chosen to utilize current signals rather than voltage signals for conveying data between the inputs and outputs of the matrix. In fact, the length of the current paths is such that it gives rise to resistance and capacitance losses which cause voltage drops which are not negligible relative to the amplitude of an AC component of a voltage signal which would transport a data.
As the switching matrices are currently realized in the form of integrated circuits, the current signals passing through them generally have a relatively low amplitude, more often of the order of a microampere. Such a current signal is thus to be amplified so as to be used by elements outside the matrix. However, as each output terminal is connected to a multiplicity of current paths which have considerable parasitic resistance and capacitance and form a substantial load seen from said output terminal, it is necessary for an amplifier intended to amplify the current signal before being made available on the output terminal to present a low input impedance so as to minimize signal losses.
Furthermore, for a signal available on an output terminal of the matrix to be effectively used by elements situated upstream of this matrix, it is desirable to construct the amplifier so that it shows a common-mode output level that is lowest possible, that is to say, that the value of the rest potential of its output terminal has to be the lowest possible. This will allow to save the widest possible variation range for an AC component of the output signal, which is representative of the information conveyed by said signal, by limiting the saturation risks of the input stages of the elements arranged downstream of the matrix.
It is an object of the invention to meet these requirements by proposing an amplifier which includes a first and a second transistor, each having a bias terminal, a transfer terminal and a reference terminal connected in series between a first and a second power supply terminal, the amplifier further including a first resistor inserted between the first power supply terminal and the transfer terminal of the first transistor, which transfer terminal is connected to the bias terminal of the second transistor and forms an input of the amplifier, the bias terminal of the first transistor being connected to a reference potential terminal.
It will be demonstrated in the following of the description that the amplifier according to the invention shows little input impedance, particularly because of the connection established between the transfer and bias terminals of the first and second transistors, respectively.
Various solutions may be envisaged for tapping an output signal from an amplifier in accordance with the invention.
In a first configuration the amplifier described above further includes a third transistor arranged as a current mirror with the second transistor, the transfer terminal of the third transistor forming an output of the amplifier.
Such a configuration permits to adjust the gain of the amplifier by the choice of a ratio of dimensions between the second and third transistors.
In a second configuration the amplifier described above further includes a third transistor arranged as a follower, whose transfer terminal forms an output of the amplifier and whose bias terminal is connected to the transfer terminal of the second transistor.
Such a configuration permits to adjust the gain of the amplifier by the choice of bias parameters of the follower incorporating the third transistor.
The following of the description will make it understood that in each of the configurations described above no current path separating the output of a ground of the amplifier includes more than one transistor, which guarantees a low common-mode level at the output of the amplifier.
An amplifier in accordance with the second configuration will advantageously include a second resistor inserted between the first and second transistors.
This second resistor generates a voltage drop which permits a larger signal excursion than the follower will receive on its input and thus permits a larger variation range of the output signal than the follower is intended to deliver.
In the description above, the amplifier shows an asymmetrical structure, that is to say, that its input and its output are intended to receive and deliver asymmetrical signals. In a number of applications it is preferable to use differential signals and symmetrical structures, notably with the aim to eliminate noise sources and noise vectors by means of compensating parasitic harmonics which are generated by components which are symmetrical on either one of the two sides of the structures involved.
The invention thus also proposes an amplifier which includes a first, a second, a third and a fourth transistor, each having a bias terminal, a transfer terminal and a reference terminal, the first and third transistors on the one hand, and the second and fourth transistors on the other hand, being connected in series between a first and a second power supply terminal, the amplifier further including a first and a second resistor, respectively, inserted between the first power supply terminal and the transfer terminals of the first and second transistors, which transfer terminals are connected to the bias terminals of the third and fourth transistors, respectively, and form a differential input of the amplifier, the bias terminals of the first and second transistors being connected together to a reference potential terminal, the third and fourth transistors together forming a differential pair.
Such an amplifier is not very noisy because of its symmetrical structure and shows an input impedance that is of the same order as that of the asymmetrical type of amplifier described above.
In a first configuration the symmetrical amplifier described above further includes a fifth and a sixth transistor arranged as current mirrors with the third and the fourth transistor, respectively, the transfer terminals of the fifth and sixth transistors forming a differential output of the amplifier.
Such a configuration permits to adjust the gain of the amplifier by the choice of a dimension ratio between the third and fifth transistors, on the one hand, and the fourth and sixth transistors on the other hand.
In a second configuration the symmetrical amplifier described above further includes a fifth and a sixth transistor which together form a differential output pair, whose transfer terminals form a differential output of the amplifier and whose power supply terminals are connected to the transfer terminals of the third and fourth transistors.
Such a configuration permits to adjust the gain of the amplifier by choosing bias parameters of the differential output pair.
The following of the description will make it understood that in each of the configurations described above no current path separating the differential output from ground of the amplifier includes a transistor anymore, which guarantees a low common-mode level at the output of the amplifier.
A symmetrical amplifier in accordance with the second configuration will advantageously include third and fourth resistors, inserted between the first and third transistors, respectively, on the one hand and the second and fourth transistors on the other.
These third and fourth resistors generate voltage drops which permit a larger excursion of the differential signal than the differential output pair will receive on its inputs, and thus authorizes a larger variation range of the output signal than said differential pair is intended to deliver.
Furthermore, it will be possible to provide the insertion of an additional resistor between the transfer terminals of the first and second transistors.
This additional resistor permits to deflect part of the current that would have passed through the first and second transistors in its absence, which current may be large if the dimensions of the third and fourth transistors are large. This permits to choose smaller dimensions for the first and second transistors without running the risk of seeing them damaged by strong currents.
As described previously, an amplifier according to the invention is particularly well adapted to being used in a switching matrix. The invention thus also relates to a switching matrix showing N signal inputs and P signal outputs, in which matrix each of the signal outputs may be connected to each of the signal inputs via at least one current path that includes at least an amplifier as described above.
These and other aspects of the invention are apparent from and will be elucidated, by way of non-limitative example, with reference to the embodiment(s) described hereinafter.